1. Field of the Invention
The present invention relates in general to a receiver of a high speed digital interface, and more particularly to a receiver having a limiting amplifier with reduced DC offset and improved impedance matching.
2. Description of the Related Art
In a receiver side of a high speed digital interface, there is a need for the amplification of high frequency low power signals. This is achieved with a dedicated differential amplifier basically consisting of a chain of low gain large bandwidth amplifiers with a parallel feedback loop.
Referring to FIG. 1, a block diagram of a conventional limiting differential amplifier in a receiver side of a high speed digital interface is shown. The differential amplifier 10 includes an input matching circuit 11, an amplification section 12 and a feedback block 13. The amplification section 12 consists of a chain of large bandwidth amplifiers to obtain enough gain in the frequencies of interest. The feedback block 13 in the DC feedback loop is connected in parallel between the inputs and outputs of said amplification section 12. All these circuit components are mounted in a differential manner. The input matching circuit 11 consists of a single resistor for the sake of simplicity. The input matching circuit 11 is mounted between two input terminals 14 and 15 receiving single-ended input signals Vinp and Vinn respectively from a preceding stage. Then corresponding single-ended output signals Voutp and Voutn are available at output terminals 18 and 19 respectively.
Feedback block 13 includes an amplifier 16 and a RC network 17 comprised of blocks 17′ for low pass filtering and 17″ to perform the summation of the direct input signals Vinp and Vinn and feedback signals Fbn and Fbp at nodes A and B at the inputs of the first amplifier of amplification section 12 as shown in the drawing. The dotting, which is made at nodes A and B, allows the desired reduction of the DC offset by the single-ended feedback signals Fbn and Fbp.
The conventional differential amplifier shown in FIG. 1 only partially reduces the DC offset, because, unfortunately, it amplifies not only the useful input signal but also any DC offset signal, coming from the previous circuits or internally generated at the input terminals of amplifier 10. The amplitude of this DC offset signal can be of the same order of magnitude or even greater than the one of the input signal itself and then can detrimentally saturate the differential output signal with invalid information. In addition, the feedback block 13, which connect the RC network 17 in parallel on the input matching circuit 11, significantly degrades the input impedance matching.